| Job Description: To design, verify and deliver cutting-edge IP for integration into customers systemson- chips. The technologies behind the IPs are in the areas of SD/MMC, MIPI, USB, PCIe and Ethernet. Will need to implement IPs based on various standards specifications. Interacts with customers to resolve issues. Will use standard tools like Verilog simulators and synthesis tools running under Linux. Must be familiar with Verilog, simulation, synthesis and good at problem solving Familiarity with modern verification techniques and Knowledge of the following is a plus: SystemVerilog, On-chip busses like AHB, OCP etc, External busses like USB, PCI etc. MIPI experience is very valuable. Version control (e.g., CVS) and scripting (perl, TCL, etc.) knowledge is required Job Responsibilities: Front end design (RTL design, documentation, verification, synthesis, and timing). To design, verify and deliver cutting-edge IP for integration into customers systems-on-chips and implement IPs based on various standards specifications. Will be required to use standard tools like Verilog simulators and synthesis tools running under Linux. Must be reasonably familiar with Verilog, simulation, synthesis and with modern verification techniques. The technologies behind the IPs are in the areas of SD/MMC, MIPI, USB, PCIe and Ethernet. Familiarity with modern verification techniques and Knowledge of the following is a plus: SystemVerilog On-chip busses like AHB, OCP etc External busses like USB, PCI etc. MIPI experience is very valuable Qualifications : BE/BS/ME/MS in E&C, EE and/or CS |
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| Desired Profile | Experience : 8 to 11 years. |
| Experience | 8 - 11 Years |
| Industry Type | Semiconductors / Electronics |
| Role | Software Developer |
| Functional Area | IT Software - Embedded, EDA, VLSI, ASIC, Chip Design |
| Education | UG - B.Tech/B.E. - Computers, Electrical, Electronics/Telecommunication, B.Sc - Computers, Electronics PG - M.Tech - Computers, Electrical, Electronics/Telecommunication, M.Sc - Computers, Electronics DOCTORATE - Doctorate Not Required |
| Location | Noida |
| Keywords | RTL, Verilog, Protocol |
| Contact |
Vanaja Karnan GNS Towers-3rd Floor 18-19/18 CL Layout BANGALORE,Karnataka,India 560029 |
| Telephone | 91-80-40809617 |
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Wednesday, 17 July 2013
Digital Design Engineer - Senior - Project Lead - Noida Location - 2 Opening(s)
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