Sr Design Engineer

Job Description

Duties will include RTL coding and modeling of SoC RF/ROM IP in System Verilog. Will own and maintain testcases to cover RF/ROM normal functionality and the modeling of power mode and collision conditions. Candidate will also be involved in DFX wrapper coding and related verification work. Will need to be able to work with RF/ROM IP customers on their verification issues. Strong written and verbal communication skills are expected.