Engineer 2, DFT

Job Description

You will join the Design-for-Test Architecture Team to develop and deploy test concepts on real silicon. In this role you will have an opportunity to understand in depth new Flash FPGA and SOC architectures. You will work closely with silicon design engineers, software engineers, yield enhancement engineers and test engineers to ensure Microsemi deploys new products with the highest quality and shortest time to market. Skills will be developed to work on multiple projects supporting key functions within the organization. Good communication and presentation skills are required.

Hardware Engineer, Power Estimation

Job Description

In this role you will be developing the power estimation tools and flows of NVIDIAs Tegra chips and platforms, from architectural level models to gate level simulations. As a developer of these tools you will be responsible for creating the technology that shapes and validates the roadmap and the accompanying investment of hundreds of millions of dollars of R&D. As a member of the Power Estimation Team, you will collaborate closely with Architects, Software Engineers, ASIC Design Engineers, and System Engineers to model the power consumption of our chips and platforms.