Job Description
In this role you will be developing the power
estimation tools and flows of NVIDIAs Tegra chips and platforms, from
architectural level models to gate level simulations. As a developer of
these tools you will be responsible for creating the technology that
shapes and validates the roadmap and the accompanying investment of
hundreds of millions of dollars of R&D. As a member of the Power
Estimation Team, you will collaborate closely with Architects, Software
Engineers, ASIC Design Engineers, and System Engineers to model the
power consumption of our chips and platforms.
