Showing posts with label ASIC Verification Engineer.System Verilog Hardware EngineerGLSPERL Python AMBA AXI. Show all posts
Showing posts with label ASIC Verification Engineer.System Verilog Hardware EngineerGLSPERL Python AMBA AXI. Show all posts

Wednesday, 18 September 2013

Senior Engineer -hardware - 2 Opening(s)

Job Description "Fluent in PERL/Python.
Experience with AMBA AHB.
Experience with USB, PCIE, DDR2, Ethernet.
Experience with AMBA AXI. "

Desired Profile "ASIC Verification Engineer.
Fluent in System Verilog.
Fluent in VMM.
Experience with GLS is a plus. ** Must have a Bachelors degree
Must have a stable career background