Showing posts with label spacer cells. Show all posts
Showing posts with label spacer cells. Show all posts

Thursday, 15 August 2013

Memory Layout Design Engineer

Job Description

  • Senior engineer position
  • Architecture development
  • Layout design + verification
  • Continuous communication with designers for clarifications of the issues
  • Provide support and guidance to the layout team
Salary: Not Disclosed by Recruiter
Industry: Semiconductors / Electronics
Functional Area: Engineering Design, R&D
Role Category: Engineering Design
Role: Senior Design Engineer
Keyskills: IO block, power gate cells, spacer cells, overlay cells, memory compiler, memory layout, memory design, memory architecture