| Job Description | *Development of high
speed SERDES for MIPI, D-PHY and M-PHY applications, with an extension
to other projects such as; USHII, USB 2.0 and USB 3.0 *Architecture definition, schematic generation, layout generation, blocks assembly, verification, and lab evaluation *Provide technical interface to customers, milestone and deliveries *Responsible for technical leadership and mentoring of junior design engineers *Will be required to seek and encourage new approaches and architectures for Market advantage *Ensure on time delivery and quality of PHY IP and active involvement in problem solving & implementing opportunities for improvement *Interfacing / interacting with other development teams Architect and lead for complex Mixed Signal SOC or large analog blocks used in multiple chips *Will be involved in the development of Mixed-Signal Designs for PHY IP, Project plans, and schedules *Designing high-speed Clock and Data-Recovery Systems (CDRs), Analog PLLs, PLLs for CRD application, high-speed clocking and clock-distribution *Experience in high speed interface sub blocks like Interpolator, Squelch, Transmitter, Receivers, Equalization and Band Gaps *Knowledge in Design of High Speed SERDES for MIPI D-PHY, M-PHYI, MPHYII, UHSII, USB2.0, USB3.0, SATAII, and PCI Express desired *Transistor level circuit design of basic building blocks like Op-amps, comparators, voltage and current reference circuits, LDOs, biasing circuits, PLL, CDR, DLL, RX, TX, ESD I/O are required *Experience in usage of IC design tools like Cadence / Mentor for Analog Circuit Design, Circuit Simulation, System Simulation, and Layout design, Physical Design, Physical Verification, Parasitic Extraction and Full Chip Verification. *Scripting Skills (Perl) as well as modeling and design skills in Verilog/Verilog ADL *Experience with deep sub-micron 40nm, 32nm, 28nm technologies is a plus *Should have experience working with cross functional teams and customers across the globe *Ability to travel internationally a plus |
| Desired Profile | Qualifications : BE/BS/ME/MS in EE and/or CS with 4 to 10+ years of relevant working experience. |
| Experience | 3 - 6 Years |
| Industry Type | Semiconductors / Electronics |
| Role | Team Lead/Technical Lead |
| Functional Area | IT Software - Embedded, EDA, VLSI, ASIC, Chip Design |
| Education | UG - B.Tech/B.E. - Computers PG - M.Tech - Computers DOCTORATE - Any Doctorate - Any Specialization, Doctorate Not Required |
| Location | Bengaluru/Bangalore |
| Keywords | Mixed Signal, Layout design, Circuit Design. Custom Design, CMOS, Analog |
| Contact |
Vanaja Karnan |
| Telephone | 91-80-40809617 |
| vanaja.k@arasan.com | |
| Website | http://arasan.com |
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Thursday, 22 August 2013
Design Engineer - Analog
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