Senior Engineer- Hardware - Verilog - 2 Opening(s)

Job Description	"Create micro-architecture, RTL design/coding, RTL integration, synthesis, FPGA implementation, Board/system level debug and validation
Desired Profile	"Logic Design RTL coding - Verilog/VHDL RTL Synthesis, Static Timing Analysis Exposure to complete flow for FPGA Development Design Debug and Validation Experience on Standard interfaces like Ethernet, DDR2/3, PCIe, USB is required Exposure to Perl/python scripting"
Experience	3 - 5 Years
Industry Type	IT-Software / Software Services
Role	Hardware Design Engineer
Functional Area	IT Hardware, Technical Support, Telecom Engineering
Education	UG - B.Tech/B.E. PG - Any Postgraduate DOCTORATE - Doctorate Not Required
Location	Pune
Keywords	Logic Design Verilog VHDL RTL SynthesisFPGA RTL codingEthernet DDR2 / 3PCIe USB
Contact	Abhishek Ranjan iGATE
Email	abhishek.ranjan@igate.com
Website	http://www.igate.com